Nearly a third of the electricity in an AI cluster never computes anything. In early 2025, data center operators reported that interconnects — the wiring that moves data between chips — were consuming nearly 30% of total cluster power, according to industry analysis published via FinancialContent. Not the processors. Not the memory. The plumbing. That figure is the shortest explanation for why silicon photonics and co-packaged optics moved from research labs into volume production in 2026, and why copper, the workhorse of computing for half a century, is being replaced by light.
The crisis is rooted in physics. When signaling runs at 224 Gbps, traditional passive copper cables now reach less than one meter, while the power needed to push electrical signals through copper has climbed sharply. The scaling law is brutal. At 100 Gbps per lane, a centimeter of copper trace dissipates measurable power; at 200 Gbps — the rate data centers are moving to, driven by AI training — the loss doubles; at 400 Gbps it doubles again. As data rates climb to serve million-GPU AI clusters, the power cost of the electrical interconnect becomes the dominant term in the system power budget. Copper didn't lose an argument. It hit a wall.
The technology replacing it is silicon photonics: building optical components — waveguides, modulators, detectors — on silicon chips using standard semiconductor manufacturing, so data travels as light pulses instead of electrical signals. It is not a new idea. In 2026, what changed was its move out of the laboratory. The question the industry had debated for a decade — whether photonic integration could be manufactured at data-center scale and cost — got its answer in shipping product.
The optics move onto the package
The industry's answer is co-packaged optics. The idea itself is simple: place the optical transceiver on the surface of the package substrate, millimeters from the switch ASIC, rather than out on the faceplate of the chassis, centimeters away. Eliminate the high-speed electrical trace. Replace it with a silicon photonic waveguide, which carries light, not electrons, and dissipates essentially no power in transit.
The efficiency gains are dramatic. Traditional electrical interconnects consumed roughly 15 to 20 picojoules per bit; current photonic integrated circuits have pushed this below 5 pJ/bit — a reduction of over 70%. Bandwidth density shows a similar jump: where copper topped out at approximately 200 Gbps per millimeter of chip edge, optical I/O now supports over 2.5 Tbps per millimeter, according to the same industry analysis. Shorten the distance, change the medium, and both problems — power and density — ease at once.
Two separate moves are bundled inside that result, and it helps to unbundle them. The first is distance: every centimeter of high-speed electrical trace burns power, so pulling the conversion point from the chassis faceplate to the package substrate removes most of the journey. The second is the medium itself: a waveguide carries light with essentially no loss in transit, where copper resists every electron the whole way. Distance explains why co-packaging matters. The medium explains why, once the optics are on the package, the numbers move by multiples rather than percentages.
The pace in the 2026 hardware generation is being set by three vendors. Using 16 integrated 6.4 Tbps optical engines and TSMC's Compact Universal Photonic Engine (COUPE) technology to stack photonic engines directly onto the switching silicon, Broadcom's Tomahawk 6 "Davisson" is the industry's first 102.4 Tbps Ethernet switch. For short-reach links, its "Direct Drive" architecture does away with the power-hungry digital signal processor altogether. NVIDIA's Quantum-X Photonics is an InfiniBand platform designed to link NVIDIA's "million-GPU" clusters, using micro-ring modulators to achieve bandwidth density over 1.0 Tbps per millimeter of chip shoreline — a fivefold increase over traditional methods — with wavelength division multiplexing packing dozens of channels onto a single fiber. NVIDIA also announced Spectrum-X Ethernet Photonics switches, each containing up to 16 co-packaged photonic integrated circuits and delivering 409.6 Tb/s with co-packaged optics integrated directly onto the ASIC package.
And underneath much of it sits TSMC's COUPE platform, the foundry foundation that entered mass production in late 2025, using SoIC-X 3D packaging to stack electrical dies directly on top of photonic dies and enabling the 2.5+ Tbps/mm densities. It is the same packaging-led moment the industry saw with Blackwell's rise, where advanced packaging became as decisive as the silicon itself. Thin-film lithium niobate modulators have pushed things further still, with bandwidths exceeding 110 GHz at drive voltages under 1 volt.
Training at scale broke the old wiring
Without co-packaged optics, the scaling laws of large language models would have hit a hard ceiling from I/O bottlenecks, according to researchers cited in the industry coverage. Training a multi-trillion-parameter model requires tens of thousands of GPUs to behave as a single coherent computational entity — the compute fabric behind everything from frontier training runs to multi-agent systems now running in production — and that is only possible if data moves between them at light speed with minimal power overhead. Every watt spent pushing electrons through copper is a watt not spent on the mathematics the building exists to perform.
The shift also enables "disaggregated" data centers. With silicon photonics, high-speed signals can travel up to 2 kilometers with negligible latency — 5 to 10 nanoseconds versus 100+ ns for DSP-based systems — allowing compute and memory to sit in different racks while behaving as one monolithic machine, according to analysis published via The Antlers American. The same architectural instinct is also driving distributed inference networks that spread compute across many sites: location no longer has to be destiny.
Sit with the disaggregation point a moment, because it redraws the building. If signals can cross 2 kilometers at 5 to 10 nanoseconds, the rack stops being the unit of design. Compute can sit where power is cheap; memory can sit where space is cheap; the two behave as one machine anyway.
A standard is what makes it a market
The market is taking shape accordingly. According to projections from analysts at IDTechEx, cited in photonics industry analysis, the co-packaged optics market will grow at a 37% compound annual rate from 2026, reaching over $20 billion by 2036. This hardware does not ship in a vacuum, either. Providing the blueprint for 3.2T and 6.4T modules now sampling for 2027 deployment, the Optical Internetworking Forum's CEI-448G framework has standardized the move to PAM6/PAM8 modulation.
Standardization matters here because hyperscalers buy on a scale that turns vendor lock-in into a strategic risk. With OIF frameworks in place, a data center operator can mix Broadcom switches, NVIDIA fabrics and TSMC-based optics with confidence that the lanes will interoperate. That in turn speeds the wider market's move away from copper.
Heat, scarce designers and the cost of waiting
The transition isn't frictionless. Start with heat. Managing heat remains the central engineering challenge of the whole transition: high-power lasers generate intense heat, and a laser inside a package crowded with AI accelerators is effectively cooking itself. Engineers have addressed it by moving the light source outside the package through the External Laser Source Form Factor (ELSFP) — keeping the silicon photonics engines at peak performance without self-destructing under AI workload thermals. And while Direct Drive removes DSPs on short-reach links, longer reaches still require signal processing, so the power savings, dramatic as they are, do not apply evenly to every link type.
The latency figures explain why disaggregation is more than a wiring preference. A difference between 5 to 10 nanoseconds and 100+ nanoseconds is not an incremental improvement; it is the difference between a signal that arrives in time to be treated as local and one that doesn't. DSP-based systems spend their nanoseconds cleaning up electrical signals — necessary work, on copper, and pure overhead once the medium changes. Remove the cleanup and the geography loosens: racks can separate, buildings can specialize, and the machine stops caring where its parts sit. That is the quiet revolution underneath the bandwidth headlines.
Then there are people. Photonic integrated circuit designers are in critically short supply — as one photonics platform builder put it, there are not enough PIC designers in the world to design all the chips the projected market needs. That bottleneck in talent could limit how quickly CPO spreads from flagship switches into the broader market. None of these frictions — heat, scarce designers, savings that vary by link type — reverses the underlying physics. They set the pace, not the direction.
For data center operators planning 2027–2028 builds, the question is when to commit. Broadcom's Davisson and NVIDIA's Quantum-X, the 2026 flagship products, are shipping in volume, and Intel's Optical Compute Interconnect chiplets form part of the ecosystem as well. The OIF standards give buyers multi-vendor confidence. AI hyperscalers, where interconnect power is already the binding constraint, are typically the early adopters; mainstream enterprise data centers will likely follow once 3.2T/6.4T modules mature and CPO pricing moves down the cost curve.
The risk of waiting is concrete. Every copper-based build locks in 15–20 pJ/bit interconnect costs for a 3–5 year hardware lifecycle, while competitors move to sub-5 pJ/bit. In an era where power availability — not chip supply — increasingly determines who can scale AI, that efficiency gap is becoming a competitive moat. With interconnects approaching a third of AI cluster power on copper, the economics now favor light decisively, and the 2026 product generation, from Davisson to Quantum-X to the COUPE platform underneath them, proves the manufacturing is real. After half a century as computing's workhorse, copper's succession is now a shipping schedule rather than a debate.
Bandwidth and heat are the same capacity problem stated twice. The compute side is defined by NVIDIA's Blackwell B200 superchips in enterprise data centers, whose rack densities set the numbers every interconnect has to serve. The thermal side has already forced its own redesign — hyperscale AI data centers are replacing air handlers with direct-to-chip liquid cooling — and photonics is best read as the matching redesign for the wires.
Sources
- GitHub (nunofernandes-plight/precision-with-light) — "From Glass to Qubits" (copper wall physics, NVIDIA Spectrum-X 409.6 Tb/s, IDTechEx 37% CAGR) — github.com
- FinancialContent — "The Dawn of the Optical Era: Silicon Photonics and the End of the AI Energy Crisis" (Jan 2026; <5 pJ/bit, 2.5 Tbps/mm, TFLN modulators) — markets.financialcontent.com
- FinancialContent/StreetInsider — "The Speed of Light: Silicon Photonics and the End of the Copper Era in AI Data Centers" (Jan 2026; Broadcom Davisson 102.4 Tbps, NVIDIA Quantum-X) — markets.financialcontent.com
- FinancialContent — "Lighting Up the AI Supercycle" (Jan 2026; TSMC COUPE mass production, OIF CEI-448G, ELSFP) — markets.financialcontent.com
- The Antlers American — "Breaking the Copper Wall: Co-Packaged Optics and Silicon Photonics Usher in the Million-GPU Era" (Jan 2026; disaggregated data centers, 2km reach) — business.theantlersamerican.com
